[OpenRISC] OR1200 Processor With 4-way set associative cache and AXI Interface

[Julius Baxter]

Hi Julius,
I am karthik, We as a team have taken OR1200 processor from Opencores
and have modified the processors direct mapped cache with 4-way set
associative cache and LRU policy. We have also modified the Bus
Interface Units of the OR1200 Processor from Wishbone protocol to AXI
Protocol. All the work done by our team is also configured
successfully on FPGA. We would like to contribute back our work to
Opencores. Please guide me how our work can be contributed to
Opencores

Hi Karthik,

That's some great sounding work.

Have you developed any new testbenches and validation infrastructure
around the modified core? That would also be extremely handy to have.
Any documentation (perhaps an update to the existing OR1200 technical
spec) would also be very welcome.

Is it possible you could submit your work as a set of patches against
a known version of the OR1200? Or is it available in a github or
similar repository somewhere online?

I'm CC'ing the OpenRISC mailing lists for further comment on this
really cool work.

Cheers

Julius

[Stefan Kristiansson]

We will prepare a documentation with our modified changes. Please tell
us how it can be uploaded to the repository with new changes.
I haven't received any response from the opencores team. If necessary we
will show the core changes in diagram. Our entire team is ready to
contribute the work we have done back to Opencores.

The way to proceed here is to send out the the patches with the
changes you have made to these mailing lists.
They will then be reviewed by the OpenRISC community and when
everybody is happy with the changes they will get accepted.

Any 'opencores team' is completely irrelevant here, the maintenance of
or1200 is a task that the OpenRISC community undertakes.

Stefan