Ouabache Designworks
2014-11-07 19:10:24 UTC
I have thought about how you could use fusesoc when doing an asic design.
Fusesoc provides
the ideal way for a project manager to create a custom orpsoc-cores that
could be
sent to the entire team to download all repositories and keep the entire
team in sync.
However there are some current shortcomings in fusesoc that would cause
problems. You should
consider these issues if you want to see fusesoc used anywhere other than
for small fpga designs.
1) Local tool install option: Installing fusesoc in the system is quick
and easy but a lot of IC
designers do not have superuser on the machines where their chips are built
and verified. In some cases they do not even have access. Some other group
will download, rebuild and simulate the entire chip on a nightly basis.
2) Sandboxing: You will have more than one design active at any time in
numerous different design environments. You MUST ensure that no IP can leak
out of one design environent and into another. Using $HOME/.cache
$HOME/.config and $HOME/.local/share is fine for most applications but
never use them for IC design.
3) File system: There is far to much IP in the world to try and fit it into
a flat file system. Try doing fusesoc list-coresand seeing 3,497 entries.
Good luck with that. You will need to switch over to a hierarchial file
system for tracking IP and the sooner the better.
4) Tools and Software: Besides IP we also need to fetch tools and software
drivers. These will also need to be stored along side the IP in a
hierarchial system. Fusesoc should be quite capable of handling these as
well.
I would like to start a discussion about these issues and any others that
would help.
John Eaton
Fusesoc provides
the ideal way for a project manager to create a custom orpsoc-cores that
could be
sent to the entire team to download all repositories and keep the entire
team in sync.
However there are some current shortcomings in fusesoc that would cause
problems. You should
consider these issues if you want to see fusesoc used anywhere other than
for small fpga designs.
1) Local tool install option: Installing fusesoc in the system is quick
and easy but a lot of IC
designers do not have superuser on the machines where their chips are built
and verified. In some cases they do not even have access. Some other group
will download, rebuild and simulate the entire chip on a nightly basis.
2) Sandboxing: You will have more than one design active at any time in
numerous different design environments. You MUST ensure that no IP can leak
out of one design environent and into another. Using $HOME/.cache
$HOME/.config and $HOME/.local/share is fine for most applications but
never use them for IC design.
3) File system: There is far to much IP in the world to try and fit it into
a flat file system. Try doing fusesoc list-coresand seeing 3,497 entries.
Good luck with that. You will need to switch over to a hierarchial file
system for tracking IP and the sooner the better.
4) Tools and Software: Besides IP we also need to fetch tools and software
drivers. These will also need to be stored along side the IP in a
hierarchial system. Fusesoc should be quite capable of handling these as
well.
I would like to start a discussion about these issues and any others that
would help.
John Eaton